don't output nested generate/endgenerate regions

src/Language/SystemVerilog/AST/GenItem.hs

@@ -17,7 +17,7 @@ import Language.SystemVerilog.AST.ShowHelp
 import Language.SystemVerilog.AST.Expr (Expr)
 import Language.SystemVerilog.AST.Op (AsgnOp)
 import Language.SystemVerilog.AST.Type (Identifier)
-import {-# SOURCE #-} Language.SystemVerilog.AST.ModuleItem (ModuleItem)
+import {-# SOURCE #-} Language.SystemVerilog.AST.ModuleItem (ModuleItem, showGenModuleItem)
 
 data GenItem
     = GenBlock Identifier [GenItem]
@@ -45,7 +45,7 @@ instance Show GenItem where
             x2 (show o2) (show e2)
             (showBlockedBranch s) -- Verilog 2001 requires this to be a block
     show (GenNull) = ""
-    show (GenModuleItem item) = show item
+    show (GenModuleItem item) = showGenModuleItem item
 
 showBareBlock :: GenItem -> String
 showBareBlock (GenBlock x i) =

src/Language/SystemVerilog/AST/ModuleItem.hs

@@ -16,6 +16,7 @@ module Language.SystemVerilog.AST.ModuleItem
     , AssignOption  (..)
     , Severity      (..)
     , AssertionItem (..)
+    , showGenModuleItem
     ) where
 
 import Data.List (intercalate)
@@ -96,6 +97,10 @@ showModportDecl (dir, ident, e) =
         then printf "%s %s" (show dir) ident
         else printf "%s .%s(%s)" (show dir) ident (show e)
 
+showGenModuleItem :: ModuleItem -> String
+showGenModuleItem (Generate genItems) = show genItems
+showGenModuleItem item = show item
+
 type PortBinding = (Identifier, Expr)
 
 type ModportDecl = (Direction, Identifier, Expr)

src/Language/SystemVerilog/AST/ModuleItem.hs-boot

@@ -1,7 +1,10 @@
 module Language.SystemVerilog.AST.ModuleItem
     ( ModuleItem
+    , showGenModuleItem
     ) where
 
 data ModuleItem
 instance Eq ModuleItem
 instance Show ModuleItem
+
+showGenModuleItem :: ModuleItem -> String