mirror of https://github.com/zachjs/sv2v.git
9 lines
205 B
Verilog
9 lines
205 B
Verilog
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module top; endmodule
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`define MODULE(str) module str; initial $display(`"hello str`"); endmodule
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`MODULE(example1)
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`MODULE(example2)
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`MODULE(example3)
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`MODULE(example4)
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`MODULE(example5)
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`MODULE(example6)
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