mirror of https://github.com/zachjs/sv2v.git
6 lines
177 B
Systemverilog
6 lines
177 B
Systemverilog
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// pattern: declarations `output a = 1` and `logic a` are incompatible due to invalid initialization at port declaration
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module top(a);
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output a = 1;
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logic a;
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endmodule
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