sv2v/test/error/instantiation_missing_ports.sv

// pattern: instantiation_missing_ports\.sv:3:14: Parse error: expected port connections before ','
module top;
    example a, c();
endmodule
improved parsing in declaration contexts - support for additional assignment statements in loop initializations - greatly improved error messaging in these contexts - decl parser takes in the ending token; significant related refactoring - pass through elaboration system tasks - removed non-blocking assignment operator precedence hack - preliminary nosim test suite for features unsupported by iverilog 2021-07-06 00:00:12 +02:00			`// pattern: instantiation_missing_ports\.sv:3:14: Parse error: expected port connections before ','`
initial pass improving decl parsing error messages - all decl tokens are given an accurate starting position - key grammar productions return token positions to facilitate the above - helpers for standardized parse error generation - replaced annoying pattern-matching type argument restrictions - moving away from dumping raw decl tokens in error messages 2021-07-03 19:23:33 +02:00			`module top;`
			`example a, c();`
			`endmodule`