mirror of https://github.com/zachjs/sv2v.git
10 lines
141 B
Verilog
10 lines
141 B
Verilog
|
module top;
|
||
|
|
reg clk;
|
||
|
|
initial begin
|
||
|
|
clk = 0;
|
||
|
|
repeat (10)
|
||
|
|
#5 clk = ~clk;
|
||
|
|
end
|
||
|
|
mod m(clk);
|
||
|
|
endmodule
|