mirror of https://github.com/zachjs/sv2v.git
9 lines
231 B
Verilog
9 lines
231 B
Verilog
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module mod(input clk);
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always @(posedge clk)
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$display($time, "posedge");
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always @(negedge clk)
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$display($time, "negedge");
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always @(posedge clk or negedge clk)
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$display($time, "edge");
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endmodule
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