mirror of https://github.com/zachjs/sv2v.git
9 lines
194 B
Verilog
9 lines
194 B
Verilog
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module top;
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parameter foo_1 = { 3'b010, 2'b01, 4'b0000 };
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parameter foo_0 = { 3'b001, 2'b00, 4'b0010 };
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initial begin
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$display(foo_0);
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$display(foo_1);
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end
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endmodule
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