mirror of https://github.com/zachjs/sv2v.git
16 lines
309 B
Verilog
16 lines
309 B
Verilog
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module top;
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function [2:0] f;
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input [2:0] n;
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f = n + 4;
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endfunction
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task t;
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begin
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$display("hello");
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$display("world");
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end
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endtask
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initial t();
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initial $display("f(0) = ", f(0));
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initial $display("f(1) = ", f(1));
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endmodule
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