mirror of https://github.com/zachjs/sv2v.git
20 lines
373 B
Systemverilog
20 lines
373 B
Systemverilog
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module top;
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task t(
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integer inp,
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output byte out1,
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shortint out2
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);
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$display("t(inp = %0d)", inp);
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out1 = inp;
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out2 = inp;
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endtask
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initial begin
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integer a;
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byte b;
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shortint c;
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a = 5;
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t(a, b, c);
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$display("a = %0d, b = %0d, c = %0d", a, b, c);
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end
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endmodule
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