mirror of https://github.com/zachjs/sv2v.git
13 lines
247 B
Verilog
13 lines
247 B
Verilog
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module top;
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reg flag;
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wire [1:0] out;
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Example example(flag, out);
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initial begin
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$monitor("%2d %b %b", $time, flag, out);
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#1 flag = 0;
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#1 flag = 1;
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#1 flag = 0;
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#1 flag = 1;
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end
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endmodule
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