mirror of https://github.com/zachjs/sv2v.git
8 lines
141 B
Verilog
8 lines
141 B
Verilog
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module top;
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if (1) begin : blk
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wire [3:0] s;
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end
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assign blk.s = 4'b1001;
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initial #1 $display("%b", blk.s);
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endmodule
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