mirror of https://github.com/zachjs/sv2v.git
18 lines
399 B
Systemverilog
18 lines
399 B
Systemverilog
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typedef struct packed {
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logic x;
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logic [3:0] y;
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logic [1:0] z;
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} Struct_t;
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module Unpacker(in, select, a, b, c);
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parameter WIDTH = 8;
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input Struct_t [WIDTH-1:0] in;
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input logic [$clog2(WIDTH)-1:0] select;
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output logic a;
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output logic [3:0] b;
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output logic [1:0] c;
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assign a = in[select].x;
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assign b = in[select].y;
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assign c = in[select].z;
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endmodule
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