mirror of https://github.com/zachjs/sv2v.git
15 lines
268 B
Verilog
15 lines
268 B
Verilog
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module top;
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parameter A = 3;
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parameter B = 4;
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reg [A*B-1:0] arr;
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initial begin : foo
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integer i;
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arr = 0;
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for (i = 0; i < A; ++i) begin
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arr[i * B +: B] = i;
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end
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$display("%b", arr);
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end
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endmodule
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