mirror of https://github.com/zachjs/sv2v.git
27 lines
727 B
Verilog
27 lines
727 B
Verilog
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`define DUMP_V(X) initial $display(`"V: X %b %0d %0d`", X, X, $bits(X));
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`define DUMP_T(X) initial begin : \dump``X \
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localparam [X - 1:0] x = 1'sb1; \
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$display(`"T: X %0d %b`", X, x); \
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end
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module mod;
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localparam integer LV1 = 1, LV2 = 2;
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parameter PT1 = 1;
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parameter integer PV1 = 100;
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parameter integer PV2 = PV1 + 3;
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parameter PT2 = 8;
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parameter [15:0] PV3 = 4;
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localparam LV3 = 5;
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localparam LT1 = 8, LT2 = 16;
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`DUMP_V(LV1) `DUMP_V(LV2) `DUMP_V(LV3)
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`DUMP_T(LT1) `DUMP_T(LT2)
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`DUMP_V(PV1) `DUMP_V(PV2) `DUMP_V(PV3)
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`DUMP_T(PT1) `DUMP_T(PT2)
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endmodule
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module top;
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mod m1();
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mod #(8, 7, 10, 4, 5) m2();
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mod #(9, 8, 11, 32, 6) m3();
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endmodule
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