mirror of https://github.com/zachjs/sv2v.git
19 lines
368 B
Verilog
19 lines
368 B
Verilog
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module top;
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function automatic [7:0] f;
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input [2:0] p;
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begin
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f = 7'b0;
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f[p+:2] = 2'b11;
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end
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endfunction
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reg [2:0] p;
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wire [7:0] q;
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assign q = f(p);
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initial begin
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$monitor("%0d, p=%b q=%b", $time, p, q);
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#1 p = 0;
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while (p != 7)
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#1 p = p + 1;
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end
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endmodule
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