mirror of https://github.com/zachjs/sv2v.git
7 lines
177 B
Verilog
7 lines
177 B
Verilog
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module Example(inp);
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localparam W = 5;
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localparam unrelated = 1;
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input wire [W - 1:0] inp;
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initial $display("%b %0d %0d", inp, $bits(inp), unrelated);
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endmodule
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