mirror of https://github.com/zachjs/sv2v.git
18 lines
440 B
Verilog
18 lines
440 B
Verilog
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`include "net_or_var.vh"
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module top;
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`TEST_ALL(reg, logic)
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`TEST_ALL(wire, wire)
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`TEST_ALL(wire logic, wire_logic)
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`TEST_ALL(wand, wand)
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`TEST_ALL(wand logic, wand_logic)
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`TEST_ALL(reg, var)
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`TEST_ALL(reg, var_logic)
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`TEST_ALL(reg, reg)
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`TEST_ALL(reg, var_reg)
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`TEST_BASE(reg [6:0], t)
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`TEST_BASE(wire [6:0], wire_t)
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`TEST_BASE(wand [6:0], wand_t)
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`TEST_BASE(reg [6:0], var_t)
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endmodule
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