mirror of https://github.com/zachjs/sv2v.git
10 lines
182 B
Verilog
10 lines
182 B
Verilog
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module top;
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reg [1:0] sel;
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wire [7:0] out;
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example e(.sel, .out);
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integer i = 0;
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initial
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for (i = 0; i < 10; i = i + 1)
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#1 sel = i;
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endmodule
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