mirror of https://github.com/zachjs/sv2v.git
60 lines
1.6 KiB
Verilog
60 lines
1.6 KiB
Verilog
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module impl;
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reg [4:0] im_x = 0;
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task im_hello;
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input integer inp;
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begin
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im_x = im_x + 1;
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$display("Hello from InterfaceM %0d %b", inp, im_x);
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end
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endtask
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initial #4 im_hello(1);
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initial #5 $display("Module got %b", im_x[0]);
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initial #4 im_hello(1);
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initial #5 $display("Module got %b", im_x[2:1]);
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initial #4 im_hello(1);
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initial #5 $display("Module got %b", im_x);
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initial im_hello(-1);
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initial $display("ModuleM got %b", im_x[0]);
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initial im_hello(-1);
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initial $display("ModuleM got %b", im_x[2:1]);
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initial im_hello(-1);
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initial $display("ModuleM got %b", im_x);
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task ia_hello;
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input integer inp;
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$display("Hello from InterfaceA %0d", inp);
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endtask
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wire [20:0] ia_x = 21'b01011_00100000_01011110;
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task ib_hello;
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input integer inp;
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$display("Hello from InterfaceB %0d", inp);
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endtask
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wire [10:0] ib_x = 11'b011_11110100;
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initial #4 ia_hello(1);
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initial #5 $display("Module got %b", ia_x);
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initial #4 ib_hello(1);
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initial #5 $display("Module got %b", ib_x);
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initial #4 im_hello(1);
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initial #5 $display("Module got %b", im_x[0]);
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initial #4 im_hello(1);
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initial #5 $display("Module got %b", im_x[2:1]);
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initial #4 im_hello(1);
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initial #5 $display("Module got %b", im_x);
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initial im_hello(-1);
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initial $display("ModuleM got %b", im_x[0]);
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initial im_hello(-1);
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initial $display("ModuleM got %b", im_x[2:1]);
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initial im_hello(-1);
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initial $display("ModuleM got %b", im_x);
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endmodule
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module top;
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impl impl();
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endmodule
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