mirror of https://github.com/zachjs/sv2v.git
15 lines
352 B
Verilog
15 lines
352 B
Verilog
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module top;
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if (1) begin : intf1
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wire [0:1][0:2] arr;
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end
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if (1) begin : intf2
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wire [0:1][0:2] arr;
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end
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assign intf2.arr[1] = 1;
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assign intf2.arr[0][0] = 0;
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initial $display("2: %b", intf2.arr);
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assign intf1.arr[1] = 6;
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assign intf1.arr[0][0] = 1;
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initial $display("1: %b", intf1.arr);
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endmodule
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