mirror of https://github.com/zachjs/sv2v.git
12 lines
259 B
Verilog
12 lines
259 B
Verilog
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module top;
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reg [7:0] z = 0;
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`define DUMP(expr, val) $display(`"expr = %b`", val);
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initial begin
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`DUMP(z, z)
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`DUMP(i.x, 8'd1)
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`DUMP(m.i.x, 8'd2)
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`DUMP(m.blk[0].x, 8'd3)
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`DUMP(m.blk[1].x, 8'd4)
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end
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endmodule
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