mirror of https://github.com/zachjs/sv2v.git
10 lines
154 B
Systemverilog
10 lines
154 B
Systemverilog
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interface Interface(output out);
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assign out = 1;
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endinterface
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module top;
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logic x;
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Interface intfs[1](x);
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initial $display(x);
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endmodule
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