mirror of https://github.com/zachjs/sv2v.git
9 lines
200 B
Verilog
9 lines
200 B
Verilog
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module top;
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initial $display("Group %0d", 8);
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generate
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genvar i;
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for (i = 0; i < 8; i = i + 1)
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initial #1 $display("Single %0d", i ** 3);
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endgenerate
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endmodule
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