mirror of https://github.com/zachjs/sv2v.git
8 lines
150 B
Verilog
8 lines
150 B
Verilog
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module top;
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function automatic [31:0] nop;
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input foo;
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nop = 32'h00000013;
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endfunction
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initial $display(nop(0));
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endmodule
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