mirror of https://github.com/zachjs/sv2v.git
49 lines
1.4 KiB
Verilog
49 lines
1.4 KiB
Verilog
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module top;
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parameter WIDTH = 1;
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if (1) begin : a
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if (1) begin : c
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reg [WIDTH*2*3-1:0] x;
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end
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end
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if (1) begin : b
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if (1) begin : d
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reg [WIDTH*5*7-1:0] x;
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end
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end
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reg [WIDTH*2*3:0] a_c_x;
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reg [WIDTH*5*7:0] b_d_x;
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if (1) begin : e
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if (1) begin : f
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reg [WIDTH*11*13-1:0] x;
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reg [WIDTH*2*3:0] a_c_x;
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reg [WIDTH*5*7:0] b_d_x;
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initial begin
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a_c_x = 1;
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b_d_x = 1;
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$display("B a.c.x %b", a.c.x);
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$display("B a_c_x %b", a_c_x);
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$display("B b.d.x %b", b.d.x);
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$display("B b_d_x %b", b_d_x);
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end
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end
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end
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reg [WIDTH*11*13:0] e_f_x;
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reg [WIDTH*2*3+1:0] e_f_a_c_x;
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reg [WIDTH*5*7+1:0] e_f_b_d_x;
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initial begin
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e_f_x = 1'sb1;
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e_f_a_c_x = 1'sbx;
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e_f_b_d_x = 1'sbz;
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$display("A a.c.x %b", a.c.x);
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$display("A a_c_x %b", a_c_x);
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$display("A b.d.x %b", b.d.x);
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$display("A b_d_x %b", b_d_x);
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$display("A e.f.x %b", e.f.x);
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$display("A e_f_x %b", e_f_x);
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$display("A e.f.a_c_x %b", e.f.a_c_x);
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$display("A e_f_a_c_x %b", e_f_a_c_x);
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$display("A e.f.b_d_x %b", e.f.b_d_x);
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$display("A e_f_b_d_x %b", e_f_b_d_x);
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end
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endmodule
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