mirror of https://github.com/zachjs/sv2v.git
9 lines
128 B
Verilog
9 lines
128 B
Verilog
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module top;
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wire [1:0] o1;
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Test1 bar(o1);
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wire o2;
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Test2 test2(o2);
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wire o3;
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Test3 test3(o3);
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endmodule
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