mirror of https://github.com/zachjs/sv2v.git
8 lines
168 B
Systemverilog
8 lines
168 B
Systemverilog
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// pattern: illegal access to range \[0:0\] of s\.x, which has type logic
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module top;
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struct packed {
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logic x;
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} s;
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initial s.x[0:0] = 1;
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endmodule
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