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7 lines
203 B
Systemverilog
7 lines
203 B
Systemverilog
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// pattern: pattern '\{..x: 1,..y: 2.\} has extra named fields \["y"\] that are not in struct packed \{..logic x;.\}
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module top;
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struct packed {
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logic x;
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} x = '{ x: 1, y: 2 };
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endmodule
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