mirror of https://github.com/zachjs/sv2v.git
6 lines
168 B
Systemverilog
6 lines
168 B
Systemverilog
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// pattern: declarations `output x` and `wire x \[1:0\]` are incompatible due to different unpacked dimensions
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module top(x);
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output x;
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wire x [1:0];
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endmodule
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