mirror of https://github.com/zachjs/sv2v.git
10 lines
174 B
Systemverilog
10 lines
174 B
Systemverilog
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// pattern: case has multiple defaults
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module top;
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case (0)
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0: wire w;
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1: wire x;
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default: wire y;
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default: wire z;
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endcase
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endmodule
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