mirror of https://github.com/zachjs/sv2v.git
13 lines
274 B
Systemverilog
13 lines
274 B
Systemverilog
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module top;
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if (1) begin : blk
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struct packed {
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logic x, y;
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} [1:0] s;
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end
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assign blk.s[0].x = 0;
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assign top.blk.s[0].y = 1;
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assign top.blk.s[1].x = 1;
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assign blk.s[1].y = 0;
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initial #1 $display("%b", blk.s);
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endmodule
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