mirror of https://github.com/zachjs/sv2v.git
13 lines
264 B
Systemverilog
13 lines
264 B
Systemverilog
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package P;
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localparam int W = 4;
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typedef logic [W - 1:0] T;
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typedef enum T {
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A = 4'b1010,
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B = 4'b0101
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} E;
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endpackage
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module top;
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initial $display("%d %d %d %b %b", $bits(P::A), $bits(P::T), $bits(P::E), P::A, P::B);
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endmodule
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