mirror of https://github.com/zachjs/sv2v.git
16 lines
263 B
Verilog
16 lines
263 B
Verilog
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module Module(x);
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input wire x;
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initial $display("Hello!");
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initial #1 $display(x);
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endmodule
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module top;
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generate
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if (1) begin
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wire x;
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Module m1(x);
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Module m2(x);
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end
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endgenerate
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endmodule
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