mirror of https://github.com/zachjs/sv2v.git
19 lines
278 B
Systemverilog
19 lines
278 B
Systemverilog
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interface Interface;
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logic x;
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endinterface
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module Module (
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Interface p
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);
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typedef struct packed {
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integer p;
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} S;
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S s = '{ p: 1 };
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initial $display("%0d %0d", s, s.p);
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endmodule
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module top;
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Interface intf();
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Module mod(intf);
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endmodule
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