mirror of https://github.com/zachjs/sv2v.git
10 lines
245 B
Systemverilog
10 lines
245 B
Systemverilog
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module top;
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localparam type T = int unsigned;
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wire [T'(32'sd32) - 1:0] x;
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function automatic [T'(32'sd32) - 1:0] foo;
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input reg [T'(32'sd32) - 1:0] inp;
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foo = inp;
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endfunction
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assign x = foo(1'sb1);
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endmodule
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