mirror of https://github.com/zachjs/sv2v.git
12 lines
166 B
Systemverilog
12 lines
166 B
Systemverilog
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module top;
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reg x;
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wire y;
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assign #5 y = x;
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initial begin
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#1 x = 0;
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#1 x = 1;
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#20 x = 0;
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#20 x = 1;
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end
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endmodule
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