mirror of https://github.com/zachjs/sv2v.git
14 lines
308 B
Verilog
14 lines
308 B
Verilog
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module top;
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wire [7:0] top;
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wire [2:0] x;
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assign x = 0;
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assign top = 8'hFF;
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initial begin
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#1;
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$display("%b %b", x, top);
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$display("%b %b", x[0], top[0]);
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$display("%b %b", x[1:0], top[1:0]);
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$display("%b %b", x[0+:1], top[0+:1]);
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end
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endmodule
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