mirror of https://github.com/zachjs/sv2v.git
25 lines
728 B
Verilog
25 lines
728 B
Verilog
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module top;
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generate
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genvar i, j;
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for (i = 1; i < 5; i = i + 1) begin
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initial begin : foo
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integer x, y;
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x = $unsigned(cast_i(1'sb1));
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y = (1 << (i + 5)) - 1;
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$display("%0d %b %b", i, x, y);
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end
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for (j = 3; j < 6; j = j + 1) begin
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initial begin : bar
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integer x;
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x = (1 << (i * j)) - 1;
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$display("%0d %0d %b", i, j, x);
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end
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end
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function signed [i-1:0] cast_i;
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input signed [i-1:0] inp;
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cast_i = inp;
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endfunction
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end
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endgenerate
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endmodule
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