mirror of https://github.com/zachjs/sv2v.git
22 lines
307 B
Systemverilog
22 lines
307 B
Systemverilog
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`default_nettype none
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typedef struct packed {
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logic [1:0] last;
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logic [1:0] first;
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} MyStruct_t;
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module Example(
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input logic [1:0] a, b,
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output logic [3:0] result
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);
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MyStruct_t s;
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assign result = s;
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assign s.last = a;
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always_comb begin
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s.first = b;
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end
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endmodule
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