mirror of https://github.com/zachjs/sv2v.git
28 lines
543 B
Verilog
28 lines
543 B
Verilog
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`default_nettype none
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module Device(
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input wire [7:0] doubleNibble,
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output wire [3:0] sum
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);
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// I would probably write the example instance2, but that is mostly me just
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// being overly cautious.
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Helper instance1(doubleNibble[7:4], doubleNibble[3:0], sum);
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wire [3:0] ignored;
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Helper instance2(
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.a(doubleNibble[7:4]),
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.b(doubleNibble[3:0]),
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.result(ignored)
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);
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endmodule
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module Helper(
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input wire [3:0] a, b,
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output wire [3:0] result
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);
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assign result = a + b;
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endmodule
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