mirror of https://github.com/zachjs/sv2v.git
37 lines
763 B
Verilog
37 lines
763 B
Verilog
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`default_nettype none
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module FSM(
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input wire a,
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output reg x,
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input wire clock, clear
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);
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parameter S_A = 32'd0, S_B = 32'd1, S_C = 32'd2;
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reg [31:0] currentState, nextState;
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always @(posedge clock)
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if(clear) begin
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currentState <= S_A;
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end else begin
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currentState <= nextState;
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end
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always @* begin
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nextState = currentState;
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case(currentState)
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S_A: nextState = a ? S_B : S_C;
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S_B: nextState = a ? S_A : S_B;
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S_C: nextState = S_A;
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endcase
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end
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always @* begin
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x = 1'b0;
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case(currentState)
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S_A: x = ~a;
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S_B: x = 1'b1;
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S_C: x = 1'b0;
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endcase
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end
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endmodule
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