mirror of https://github.com/zachjs/sv2v.git
29 lines
466 B
Verilog
29 lines
466 B
Verilog
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`default_nettype none
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module top;
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reg clock, clear;
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wire [3:0] data;
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Device dut(
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.clock(clock),
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.clear(clear),
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.data(data)
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);
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initial begin
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clock = 1;
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forever #5 clock = ~clock;
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end
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initial begin
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$monitor($time, " data: %h", data);
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clear = 1'b1;
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repeat(3) @(posedge clock);
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clear = 1'b0;
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repeat(20) @(posedge clock);
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$finish;
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end
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endmodule
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