mirror of https://github.com/zachjs/sv2v.git
41 lines
932 B
Verilog
41 lines
932 B
Verilog
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module main;
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reg [2:0] foo_x_1;
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reg [2:0] foo_x_0;
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reg [1:0] foo_y_2;
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reg [1:0] foo_y_1;
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reg [1:0] foo_y_0;
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wire [5:0] foo_x;
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wire [5:0] foo_y;
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assign foo_x = {foo_x_1, foo_x_0};
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assign foo_y = {foo_y_0, foo_y_1, foo_y_2};
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reg foo_z;
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wire [12:0] foo;
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assign foo = {foo_x, foo_y, foo_z};
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initial begin
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$monitor($time, " %b %b %b %b %b %b %b %b",
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foo, foo_x, foo_y, foo_z,
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foo_x_0, foo_x_0[0], foo_y_0, foo_y_0[0]);
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#1; foo_z = 0;
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#1; {foo_y_0, foo_y_1, foo_y_2} = 0;
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#1; foo_y_0 = 1'sb1;
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#1; foo_y_1 = 1'sb1;
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#1; foo_y_1[1] = 0;
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#1; foo_y_0[0] = 1;
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#1; foo_y_0[1] = 1;
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#1; {foo_x_1, foo_x_0} = 0;
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#1; foo_x_0 = 1'sb1;
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#1; foo_x_1 = 1'sb1;
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#1; foo_x_1[1] = 0;
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#1; foo_x_0[0] = 1;
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#1; foo_x_0[1] = 1;
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end
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endmodule
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module top;
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endmodule
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