mirror of https://github.com/zachjs/sv2v.git
15 lines
241 B
Verilog
15 lines
241 B
Verilog
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module top;
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function automatic f;
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input unused;
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f = 0;
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endfunction
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function automatic g;
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input unused;
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g = f(0);
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endfunction
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localparam A = g(0);
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initial $display("%b", A);
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endmodule
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