mirror of https://github.com/zachjs/sv2v.git
12 lines
190 B
Verilog
12 lines
190 B
Verilog
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module top;
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reg [1:0] a[1:0];
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reg [1:0] b[1:0];
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reg [1:0] c[1:0], d[1:0];
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reg [1:0] e[1:0], f[1:0], g;
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reg [1:0] h, i[1:0];
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reg [1:0] j;
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reg [1:0] k;
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endmodule
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