mirror of https://github.com/zachjs/sv2v.git
15 lines
292 B
Verilog
15 lines
292 B
Verilog
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module Example;
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parameter FOO = 1;
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initial $display("%0d", FOO);
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endmodule
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module top;
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Example e[5:0]();
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defparam e[0].FOO = 1;
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defparam e[1].FOO = 2;
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defparam e[2].FOO = 4;
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defparam e[3].FOO = 8;
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defparam e[4].FOO = 16;
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defparam e[5].FOO = 32;
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endmodule
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