mirror of https://github.com/zachjs/sv2v.git
26 lines
730 B
Verilog
26 lines
730 B
Verilog
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module top;
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wire input_a, input_b;
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wire [1:0] input_c;
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wire [5:0] input_d;
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wire [1:0] output_a, output_b;
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wire [5:0] output_c, output_d;
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mod m(
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input_a, input_b, input_c, input_d,
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output_a, output_b, output_c, output_d
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);
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integer i;
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localparam bits = $bits({input_a, input_b, input_c, input_d });
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assign {input_a, input_b, input_c, input_d} = i;
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initial begin
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$monitor(
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"%03d (%b, %b, %b, %b) -> (%b, %b, %b, %b)",
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$time,
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input_a, input_b, input_c, input_d,
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output_a, output_b, output_c, output_d
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);
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repeat(3)
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for (i = 0; i < 2 ** bits; i = i + 1)
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#1;
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end
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endmodule
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