mirror of https://github.com/zachjs/sv2v.git
12 lines
232 B
Verilog
12 lines
232 B
Verilog
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module Example(inp);
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input [19:0] inp;
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initial #1 $display("%b", inp);
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endmodule
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module top;
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Example e1({20 {1'sb0}});
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Example e2({20 {1'sb1}});
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Example e3({20 {1'sbx}});
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Example e4({20 {1'sbz}});
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endmodule
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