mirror of https://github.com/zachjs/sv2v.git
10 lines
198 B
Verilog
10 lines
198 B
Verilog
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module top;
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initial begin
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$display("A %0d", 1);
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$display("B %0d", 2);
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$display("C %0d", 4);
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$display("B %0d", 2);
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$display("A %0d", 1);
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end
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endmodule
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