mirror of https://github.com/zachjs/sv2v.git
9 lines
205 B
Systemverilog
9 lines
205 B
Systemverilog
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// pattern: declaration i uses interface name I where a type name is expected
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// location: interface_name_var.sv:7:12
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interface I;
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logic [3:0] x;
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endinterface
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module top;
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if (1) var I i;
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endmodule
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